StefanSchippers / xschem
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
- Repository stars
- 510All-time #61,075
- Fork
- 52
- Last push
- updated 1 days ago
- Repository created
- since 2020
About
A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.Summarised by AI from the README; the original prevails
Author description: A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
Basic listing based on official public information; functionality has not been independently evaluated.
Check before adopting
- No license declared: commercial use and redistribution terms are unknown.
- Pricing
- Pricing not verifiedCheck current official software, hosting, model and infrastructure pricing.